EFM32G-DK3550【PDF 123/467 页】KIT DEVELOPMENT EFM32 GECKO

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...the world's most energy friendly microcontrollers

12.4 Register Map

The offset register address is relative to the registers base address.

Offset

Name

Type

RW

W1

R

Description

Control Register

Command Register

Synchronization Busy Register

12.5 Register Description

12.5.1 WDOG_CTRL - Control Register (Async Reg)

For more information about Asynchronous Registers please see Section 5.3 (p. 18) .

Offset

0x000

Reset

Access

Name

Bit Position

Bit

Name

Reset

Access

Description

31:14

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

13:12

CLKSEL

0x0

RW

Watchdog Clock Select

Selects the WDOG oscillator, ie. the clock on which the watchdog will run.

Value

0

1

2

Mode

ULFRCO

LFRCO

LFXO

Description

ULFRCO

LFRCO

LFXO

11:8

PERSEL

0xF

RW

Watchdog Timeout Period Select.

Select watchdog timeout period.

Value

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Description

Timeout period of 9 watchdog clock cycles.

Timeout period of 17 watchdog clock cycles.

Timeout period of 33 watchdog clock cycles.

Timeout period of 65 watchdog clock cycles.

Timeout period of 129 watchdog clock cycles.

Timeout period of 257 watchdog clock cycles.

Timeout period of 513 watchdog clock cycles.

Timeout period of 1k watchdog clock cycles.

Timeout period of 2k watchdog clock cycles.

Timeout period of 4k watchdog clock cycles.

Timeout period of 8k watchdog clock cycles.

Timeout period of 16k watchdog clock cycles.

Timeout period of 32k watchdog clock cycles.

Timeout period of 64k watchdog clock cycles.

Timeout period of 128k watchdog clock cycles.

Timeout period of 256k watchdog clock cycles.

2011-04-12 - d0001_Rev1.10

123

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